Interface Controller - PHY IP / amba ahb / apb/ axi / amba ahb / apb IP Core

The SPI2AHB core implements an SPI slave to AHB-Lite master bridge. It allows an external SPI master to perform read or write access to any memory-map...

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SPI to AMBA AHB Master Bridge

The Veriest SPI to AMBA AHB Master Bridge Design IP offers a simple solution to provide "backdoor" access from external SPI master devices to the embe...

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SPI to AXI Bridge

The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...

154

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Hs-Mode I2C Controller - 3.4 Mbps, Master w/FIFO

The Digital Blocks DB-I2C-M-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus...

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Hs-Mode I2C Controller - 3.4 Mbps, Slave w/FIFO

The Digital Blocks DB-I2C-S-Hs-Mode I2C Slave Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO) or an...

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eSPI & SPI Master Controller w/FIFO

The Digital Blocks DB-eSPI-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...

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eSPI & SPI Slave Controller w/FIFO

The Digital Blocks DB-eSPI-SPI-S-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...

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AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA

The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash...

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AXI Multilayer Interconnect

The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The AXI fabric ...

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AXI Subsystem

The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces...

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AXI to AHB Lite Bus Bridge

The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...

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AXI to APB Bridge

The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI bus. The highly con...

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AXI to APB Bus Bridge

The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one ...

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AXI2APB Bridge

Truechip's AXI2APB IP provides chip designers and architects, an efficient way to connect AXI & APB based IPs with reduced latency, power, and area....

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CXS to UCIe Bridge IP

SmartDV’s CXS to UCIe Bridge IP enables seamless connectivity between chiplet-based designs and traditional SoC architectures by bridging AMBA CXS int...