Interface Controller - PHY IP / amba ahb / apb/ axi / amba ahb / apb IP Core

The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The AXI fabric ...

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AXI Performance Subsystem

The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needing high performance. ...

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AXI Subsystem

The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces...

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AXI to AHB Lite Bus Bridge

The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...

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AXI to APB Bridge

The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI bus. The highly con...

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AXI to APB Bus Bridge

The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one ...